1. Field of the Invention
The present invention relates to a testing method for a large-scale network composed of a plurality of semiconductor devices, in particular, to a scanning device for performing network testing for a scan path formed by interconnecting semiconductor devices to be tested.
2. Description of the Related Art
In recent years, the use of the parallel computer system for high-speed computer processing having a plurality of interconnected CPUs (Central Processing Units) has been increasing. In a parallel computer system, which is provided with a network to connect between a plurality of CPUs, an amount of the wiring materials used for organizing a network increases with an increasing number of CPUs used. Alternatively, an amount of wiring is increased to achieve high performance by raising a transfer rate over a network between CPUs.
Consequently, complicated wiring is installed in a network in a parallel computer system, and this brings difficulties in testing the connection state thereof. From practical and economical viewpoints, an increase in an amount of hardware for testing should be as small as possible, and a shorter testing time is desired.
As a standard testing method for a parallel computer system of this type, which is intended for facilitating reducing an amount of testing hardware, there is an established standard, IEEE Std 1149.1 (the Institute of Electrical and Electronics Engineers Standard Test Access Port and Boundary-Scan Architecture). The testing method in accordance with this standard is generally called a "JTAG-SCAN (Joint Test Action Group-Scan) method.
The JTAG-SCAN method is characterized in that register information in an LSI (Large Scale Integration) circuit is fetched using a general purpose port called TAP (Test Access Port), thereby allowing an entire state of the LSI to be observed/controlled. This method enables this function to be used even for a printed circuit board with LSIs mounted thereon, and thus is suitable for testing a system including a plurality of semiconductor devices such as an LSI.
Normally, TAP includes the five signal lines of TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data Input), TDO (Test Data Output), and TRST (Test Reset).
TCK represents a port for testing a clock signal, and TMS represents a port for a signal which changes a state of a TAP controller. The TAP controller thus referred to is a finite state machine (finite automaton) for controlling a sequence of a circuit operation in JTAG testing.
Additionally, TDI represents an input port for instructions or data for testing, TDO represents an output port to output test data, and TRST represents a port for initializing the TAP controller. Among them, TRST is an optional port, and so is not necessarily used.
However, conventional JTAG testing of a large-scale system involves the following problems.
A parallel computer network shown in FIG. 1A is assumed to be a virtual testing system to be tested. An LSI called RTC (Routine Controller) 1 is arranged on each node in the network shown in FIG. 1. Each RTC 1 is connected to its own CPU, not shown, for controlling the communication between those CPUs. In other words, a solid line between RTCs 1 shows wiring in a network between CPUs.
Further, each RTC 1 is provided with a JTAG I/F (JTAG Interface) composed of a signal line that corresponds to the TAP described above. It should be noted that the JTAG I/F is described as JTAG only in FIG. 1A, and signal lines corresponding only to TDI and TDO of each RTC 1 are shown therein.
In the parallel computer network shown in FIG. 1A, RTCs 1 are arranged in a two-dimensional plane, although they are actually arranged in a torus-like configuration in many cases. However, for simplicity, an outline of JTAG testing will be explained hereinafter using the schematic configuration shown in FIG. 1A.
In general JTAG testing, as shown in FIG. 1B, a scan loop (a scan path) is created by connecting input and output ports, TDIs and TDOs, in a chain-like configuration. Thus, an entire system is simultaneously tested under the control of a scan engine (SCANE) 2.
However, the JTAG testing shown in FIG. 1B has a problem that there is no flexibility in the system configuration. The scan loop is determined so as to include all RTCs 1 in the design of a circuit. For this reason, a node with no RTC 1 provided requires a change of wiring, and the number of RTCs 1 cannot be reduced without difficulties. Additionally, enhancement of the system by the addition of an RTC 1 also requires a change in wiring. Consequently, any change of the system configuration requires significant cost.
Further, with JTAG testing as described above, all RTCs 1 are included in a scan loop. This causes the problem that a long time is required for the scan testing. For example, a parallel computer system of the type AP3000 is provided with up to a maximum of 1,024 CPUs, and has the same number of RTCs 1 corresponding thereto. When register information for a part of this large-scale system is desired to be read out, reading the information through all RTCs 1 is a waste of time.
As described above, with JTAG testing, a general low-cost and high-speed testing method for a large-scale system has yet be established.